Job Description

PLEASE HAVE CURRENT EDA/SEMI TYPE EXPERIENCE!

ASIC Design Verification Engineer – UVM specialist, Bay area #8016

In this role, you will not be doing “Design Verification”, but you need to have verified designs or been deeply involved in the process.

My client is a very promising well-funded startup at the cutting edge of integrating LLMs with chip design. Their team is composed of experts in the fields of AI, software development, and semiconductor design. The founders have an amazing background and pedigree, perfect for this venture.

This totally new approach to chip design is a game changer and with their strong foundation and existing customer base, they are positioned to redefine the landscape of chip design.

Job Description:

They are looking for skilled and passionate Verification Engineers or Chip Designers who have significant experience with VLSI front-end design flows, specifically UVM, to collaborate closely with their ML and software teams. In this unique role, you will apply LLM’s for DV; you will work on advanced technologies that leverage your design verification experience with ML for innovative chip design solutions; You will have the opportunity to learn from experienced ML leads and directly contribute to projects for their existing customers.

This position is ideal for a chip designer who is eager to push beyond traditional roles and explore the frontier of AI-integrated semiconductor design. This terrific opportunity will give you the opportunity to make a real and significant contribution, as they unleash this existing, yet totally new approach to CHIP DESIGN.

Key Responsibilities:

• Collaborate with ML/AI and software teams to develop advanced, AI-driven chip design solutions.
• Work with customers to best understand their needs with the team
• Learn from and work closely with strong ML leads to understand and implement cutting-edge technologies in chip design.
• Engage directly with customer projects, applying your expertise to develop practical and innovative solutions.
• Contribute to the integration of LLM technologies into the chip design process, enhancing design efficiency and performance.
• Stay updated with the latest advancements in chip design and AI/ML technologies to continually improve methodologies and solutions.

Qualifications:

• 3-10 years hands on experience working on or doing chip verification using UVM
• A thorough understanding of UVM and SysVerilog
• Knowledge in Verification and writing UVM and running it for design
• Working knowledge and experience implementing EDA tools
• Strong experience in chip design, including a thorough understanding of design verification through tapeout.
• Solid programming skills (e.g., Python, C/C++, Verilog, SystemVerilog).
• Experience or interest in AI/ML technologies, especially in the context of LLMs, is highly desirable.
• Strong problem-solving abilities and a proactive attitude toward learning and innovation.
• Excellent communication skills and the ability to work effectively in a team-oriented environment.
• SW/ML a plus
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

As a young startup funded by top VCs in Silicon Valley, this is a unique opportunity that you can’t really get anywhere else:

• Personal impact — The opportunity to build something from the ground up and define a new product for an industry that is at the core of the modern technological revolution.
• Access to unique learning opportunities — With the Allen Institute for AI (AI2) as a co-founder, our team gets access to numerous talks by leading AI researchers/paper authors, knowledge sharing amongst the community of hundreds of engineers working for AI2 companies, and much more. As a part of the multi-disciplinary team, you get to interact with people from very different backgrounds (from chip design to AI to software engineers).
• Founding title — You will be one of our first hires. For the rest of our days, no matter how many thousands of people join after you, you will always have that honor and distinction.
• Early-stage equity — Early-stage risk comes with early-stage equity for you. And none of us would be here if we didn’t think our company would create tremendous value over time.
• Benefits — In spite of being an early-stage company, taking care of our team is a priority for us. From health insurance to catered lunches, we continue to add unique benefits.

To learn more about this and other openings, contact Mark Gilbert anytime by email, mark@eda-careers. com or call 305-598-2222x3 . Please include your resume so we can have a more precise conversation.

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